The high voltage integrated circuit (HVIC) is necessary for high voltage applications, such as motor, ballast, two inductor one capacitor (LLC), and cold cathode fluorescent lamp (CCFL). For example, referring to FIG. 1, a high-side power transistor T1 and a low-side power transistor T2 of a half H-bridge circuit are controlled by gate control signals UG and LG provided by a controller IC 10, respectively. The gate control signals UG and LG are generated responsive to non-overlapping switch signals HIN and LIN, respectively. The direct-current (DC) input voltage VIN for the half H-bridge circuit may be up to 300-600 V or higher. In order to reduce the number of high-voltage circuit components used in the controller IC 10 and lower the voltage to which the high-side circuit will be subjected, the high-side circuit is formed in an ultra-high-voltage floating well 12, which is electrically coupled to the switching node LX of the half H-bridge circuit, and the voltage VLX of the switching node LX is used as the reference potential of the high-side circuit. The switch signals HIN and LIN are referenced to a low-voltage logic signal generated at the ground terminal GND. Then, the switch signal HIN is shifted to a higher level to generate the gate control signal UG. As the reference potential of the high-side circuit is not the voltage at the ground terminal GND but the voltage VLX at the switching node LX, the foregoing structure is known as a floating gate driver.
To shift the level of the switch signal HIN, a pulse generator 14 detects the rising edge and the falling edge of the switch signal HIN to trigger a set signal Set and a reset signal Reset, respectively, both of which are short-pulse signals, and a level shifter 16 translates the set signal Set and the reset signal Reset into the set input signal S and the reset input signal R of an SR flip-flop 18 to turn on and turn off the switch signal Q in reference to the voltage VLX. Therefore, the switch signals Q and HIN have the same logic state but are at different voltage levels. In the level shifter 16, the input transistors M1 and M2 are configured to transmit the set signal Set and the reset signal Reset to the output terminals AA and BB, respectively, and resistors R1 and R2 serve as loads of the input transistors M1 and M2, respectively. With the output terminals AA and BB being connected to the power input terminal Vb via the resistors R1 and R2, respectively, the input transistors M1 and M2 must be high-voltage transistors, the circuit design of which, therefore, entails a compromise between chip area and breakdown voltages. The input transistors M1 and M2 require large area if formed outside the ultra-high-voltage floating well 12, and may cause significant cross talk issue if formed in the ultra-high-voltage floating well 12, as a result of their proximity to each other.
U.S. Pat. No. 7,236,020 uses a single-end level shifter instead to translate the set signal Set and the reset signal Reset, and the translated signals are output from a same output terminal of the single-end level shifter to a D flip-flop in order to generate a level-shifted switch signal. Since the single-end level shifter includes only one input transistor, the circuit area of the level shifter can be significantly reduced, and cross talk between the conventionally required two input transistors is eliminated. Nevertheless, the single-end level shifter is disadvantaged by low noise immunity. For example, referring back to FIG. 1, the bootstrap capacitor Cb coupled between the power input terminal Vb and the switching node LX tends to introduce transient variation of the voltage VLX into the supply voltage Vb, and transient variation of the voltage Vb will in turn charge or discharge the parasitic capacitance Cp1 of the input transistor M1, thus generating noise at the output terminal AA. Since the single-end level shifter outputs the translated set signal Set and the translated reset signal Reset through the common output terminal AA, the aforesaid noise may lead to erroneous action of the D flip-flop or even cause the power transistors T1 and T2 to be turned on at a same time. Should the latter occur, the high-voltage DC power supply VIN will be directly short to the ground terminal GND.
Therefore, it is desired a circuit and a method for improving noise immunity of a single-end level shifter in a floating gate driver.